1. Field of Invention
The present invention relates to a semiconductor overlapped PN structure and a manufacturing method thereof, in particular to such structure and method that provide flexibility for adjusting breakdown voltages of semiconductor devices.
2. Description of Related Art
It is often required for a semiconductor device to be implanted with P type impurities and N type impurities in a substrate. FIG. 1 illustrates by top view, a prior art impurities implanted region in a substrate, which can be used in a high voltage device. As shown in the figure, the impurities implanted region includes a P type well 11 and an N type well 12 separated from each other; that is, the region implanted with the P type impurities does not overlap with the region implanted with the N type impurities. During a diffusion process after the implantation process, ions of the P type well 11 and ions of the N type well 12 will diffuse toward each other to form a diffusion region 13 between the P type well 11 and the N type well 12. The concentration of the P type impurities and the N impurities in the diffusion region 13 determines a breakdown voltage of the semiconductor device. Different devices may require different breakdown voltages, but due to limitations resulting from transistor device design, there is not too much room to adjust the concentration of the P type impurities and the N type impurities. Thus, if it is required to provide different devices with different breakdown voltages in the same wafer, one has to use additional masks and perform one or more additional ion implantation processes so that different diffusion regions 13 can be formed for different devices. As such, the manufacturing process is more complex which involves a higher cost, and the complexity and cost further increase as the number of the devices in a wafer increases.
FIG. 2 illustrates by top view, another prior art impurities implanted region in the substrate, wherein the impurities implanted region includes a P type well 21 and an N type well 22 which overlap with each other to form an overlapped region 23; that is, two regions respectively implanted with the P type impurities and the N type impurities overlap with each other, so the overlapped region 23 is implanted with both the P type and N type impurities. Similarly, if it is required to provide different devices with different breakdown voltages in the same wafer, one has to use additional masks and perform one or more additional ion implantation processes so that different overlapped regions 23 can be formed for different devices. As such, the prior art also requires a more complex manufacturing process and higher cost.
In view of above, to overcome the drawbacks in the prior art, the present invention proposes a semiconductor overlapped PN structure and a manufacturing method thereof which flexibly provide different devices with different breakdown voltages in the same wafer, in which it is not required to adjust the concentration of the impurities or increase any additional mask and ion implantation process.